SYNOPSYS SILICON-SEA-BELT DESIGN CONTEST 2002
The digital design contest for
students using HDL (VHDL or Verilog)
will be held by the Information Engineering Department
of
the Univ. of the Ryukyus.
Pre-selected presenters will be invited
to the Island Okinawa coming 2002/MARCH
for presenting their summary.
Please join the contest and enjoy Okinawa!
Target: Error Correction Circuit Using Difference-set Cyclic code
Who can join: the team of 1-3 University or college students
If you want to join, please let wada@ie.u-ryukyu.ac.jp know until 02/Jan/18.
Final Report dead line : 2002/Feb/15.
Conference: Okinawa @ 2002/March/8