===Load constant=====
cal cal r3,r1,111 r3=r1+111 compute address lower
cal cal r3,r0,111 r3=111 special case of r0
cau cal r3,r1,111 r3=r1+(111<<16) compute address upper
cau cal r3,r0,111 r3=(111<<16) special case of r0
cal r3,r0,lower(const); cau r3,r3,higer(const)
により、r3に32bit定数をloadできる
compute address の場合は r0 が特別扱いされる
cax cax r3,r1,r2 r3=r1+r2 add と同じ
===Load =====
l l r3,4(r1) r3=*(r1+4) load word, 16bit offset
lu l r3,4(r1) r3=*(r1+4),r1=r1+4 with update
lx lx r3,r1,r2 r3=*(r1+r2) load word indexed
lux lx r3,r1,r2 r3=*(r1+r2),r1=r1+r2 with update
lbz lbz r3,4(r1) r3=(char *)(r1+4) load byte
lbzu lbz r3,4(r1) r3=(char *)(r1+4),r1=r1+4 with update
lbzx lbz r3,r1,r2 r3=(char *)(r1+r2) load byte indexed
lbzux lbz r3,r1,r2 r3=(char *)(r1+r2),r1=r1+r2 with update
===Store =====
st st r3,4(r1) *(r1+4)=r3 store word, 16bit offset
stu st r3,4(r1) *(r1+4)=r3,r1=r1+4 with update
stx stu r3,r1,r2 *(r1+r2)=r3
stux stu r3,r1,r2 *(r1+r2)=r3,r1=r1+r2
stb stb r3,4(r1) (char *)(r1+4)=r3
stbx stbux r3,r1,r2 (char *)(r1+r2)=r3
stbu stbu r3,4(r1) (char *)(r1+4)=r3,r1=r1+4
stbux stbux r3,r1,r2 (char *)(r1+r2)=r3,r1=r1+r2
===Add =====
a a r3,r1,r2 r3=r1+r2 add
a. a. r3,r1,r2 r3=r1+r2 add and set flag CR0
ao ao r3,r1,r2 r3=r1+r2 add with over flow check
ao. ao. r3,r1,r2 r3=r1+r2 add with over flow and set flag CR0
ae[.] ae r3,r1,r2 r3=r1+r2+c add with carry [set flag CR0]
ai[.] ai r3,r1,-45 r3=r1+(-45) add immediate [set flag CR0]
16bit singed constatnd
sf[o.] sf r3,r1,r2 r3=-r1+r2 subtract from
sfi[o.] sfi r3,r1,3 r3=-r1-3 subtract from immediate
neg[o.] r3,r1 r3=-r1 negation
muls r3,r1,r2 r3=r1*r2 multiply short
muli r3,r1,10 r3=r1*10 multiply immediate
div r3,r1,r2 r3=r1/r2 divide unsigned
divs r3,r1,r2 r3=r1/r2 divide signed
ame[o.] ame r3,r1 r3=r3+c-1 Add minus one extented
aze[o.] aze r3,r1 r3=r1+c add 0 with carry
extsb extsb r3,r1 r1=(signed char) sign extend signed byte
extsh extsh r3,r1 r1=(signed cahr) sign extend double byte
extsw extsw r3,r1 r1=(signed cahr) sign extend full word
===Branch =====
bl label branch and link
LR=return address
mfspr mfspr r0,LR r0=LR move from special register
bl からの return に使う
b b BO_IF,CR0_EQ,label branch conditional
bcc bcc BO_IF,CR0_GT,label brach conditional to counter register
bccl bcc BO_IF,CR0_GT,label brach conditional to counter register
save return address to link register
bcr[l] bcr BO_IF,CR0_GT,label brach conditional to link register
条件分岐は、
CR0..CR7 でフラグを指定し、BO_IF で条件を指定する
BO_IF branch on true
BO_IF_NOT branch on false
BO_ALLWAYS branch always
BO_dCTR_NZERO decrement Count Reigster and bracn on non zero
BO_dCTR_ZERO_AND decrement Count and bracn on zero and conditon
BO_dCTR_NZERO_AND decrement Count and bracn on non zero and cond
CR0_GT >
CR0_LT <
CR0_EQ =
CR0_SO overflow
===Compare =====
cmpli cmpli 1,r3,0x0000 compare r3 and immidiate value
as unsigned and set flag 1
cmpi cmpi 1,r3,0x0000 compare r3 and immidiate value
as signed and set flag 1
cmpl cmpl 1,r3,r4 compare r3 and r4 and set flag 1
as unsigned
cmp cmp 1,r3,r4 compare r3 and r4 and set flag 1
as signed
mfcr mfcr r3 move from condtion register
rlinm r3,r3,6,31,31 rotate left word then AND with mask
(r3>>6 & 1) mask = 31..31
===Logical =====
andil. andil. r3,r1,11 r3=r1&11 And immideate lower
andiu. andiu. r3,r1,11 r3=r1&(11<<16) And immideate lower
16bit singed constatnd
and and r3,r1,r2 r3=r1&r2
xor xor r3,r1,r2 r3=r1^r2
nand nand r3,r1,r2 r3=~(r1|r2)
nor nor r3,r1,r2 r3=~(r1&r2)
andc andc r3,r1,r2 r3=~(r1& ~r2)
orc orc r3,r1,r2 r3=~(r1| ~r2)