library IEEE;
use IEEE.std_logic_1164.all;

entity  FULL_ADDER  is
    port (  A, B, CIN  : in  std_logic;
	    S, CO      : out std_logic);
end FULL_ADDER;

architecture  STRUCTURE  of  FULL_ADDER  is
component  HALF_ADDER  port  ( A, B    :  in  std_logic;
				S, CO  : out  std_logic);
end component;
signal  U0_CO, U0_S, U1_CO  :  std_logic;
begin
    U0  :  HALF_ADDER port map (A, B, U0_S, U0_CO);
    U1  :  HALF_ADDER port map (U0_S, CIN, S, U1_CO);
    CO <= U0_CO or U1_CO;
end  STRUCTURE;