library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

entity ALU is
    port(Sel     :  in  unsigned(4 downto 0);
	 CarryIn :  in  std_logic;
	 A, B    :  in  unsigned(7 downto 0);
	 Y       :  out unsigned(7 downto 0) );
end entity ALU;

architecture COND_DATA_FLOW of ALU is
begin

    ALU_AND_SHIFT:
    process (Sel, A, B, CarryIn)
	variable Sel0_1_CarryIn  : unsigned(2 downto 0);
	variable LogicUnit, ArithUnit,
		 ALU_NoShift     : unsigned(7 downto 0);
    begin
	---------------------------
	-- Logic Unit 
	---------------------------

 -- Here please complete the Logic Unit!

	---------------------------
	-- Arithmetic Unit
	---------------------------
	Sel0_1_CarryIN := Sel(1 downto 0) & CarryIN;

 -- Here, please complete the Arithmetic Unit

	---------------------------
	-- Mutiplex
	---------------------------
	LA_MUX: if (Sel(2) = '1') then
	    ALU_NoShift := LogicUnit;
        else
	    ALU_NoSHift := ArithUnit;
        end if LA_MUX;
	---------------------------
	-- Shift operation
	---------------------------
	SHIFT: case Sel(4 downto 3) is
	    when "00"    =>  Y <= ALU_NoSHift;
	    when "01"    =>  Y <= Shift_left(ALU_NoShift, 1);
	    when "10"    =>  Y <= Shift_right(ALU_NoShift, 1);
	    when "11"    =>  Y <= (others => '0');
	    when others  =>  Y <= (others => 'X');
        end case SHIFT;
    end process ALU_AND_SHIFT;
end architecture COND_DATA_FLOW;