library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FSM23 is
    port ( Clock, Reset  : in  std_logic;
	   Control       : in  std_logic;
	   Y             : out integer range 0 to 4 );
end entity FSM23;

architecture RTL of FSM23 is
    type StateType is (ST0, ST1, ST2, ST3);
    signal CurrentState, NextState : StateType;
begin
    ----------------------
    -- NEXT STATE LOGIC & OUTPUT LOGIC
    ----------------------
    COMB: process (Control, CurrentState)
    begin
	case CurrentState is
	    when ST0 => 
		Y <= 1;
		NextState <= ST1;
            when ST1 =>
		Y <= 2;
		if (Control ='1') then NextState <= ST2;
		else                   NextState <= ST3;
		end if;
            when ST2 =>
		Y <= 3;
		NextState <= ST3;
            when ST3 =>
		Y <= 4;
		NextState <= ST0;
            when others => 
		Y <= 1;
		NextState <= ST0;
        end case;
    end process COMB;

    ----------------------
    -- CURRENT STATE LOGIC
    ----------------------
    SEQ: process (Clock, Reset)
    begin
	if (Reset ='1') then
            CurrentState <= ST0;
        elsif rising_edge(Clock) then
	    CurrentState <= NextState;
        end if;
    end process SEQ;
end architecture RTL;