library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FSM24 is
    port ( Clock, Reset  : in  std_logic;
	   Control       : in  std_logic;
	   Y             : out integer range 0 to 4 );
end entity FSM24;

architecture RTL of FSM24 is
begin
    ----------------------
    -- CURRENT & NEXT STATE LOGIC & OUTPUT LOGIC
    ----------------------
    ALL_IN_1: process (Clock, Reset)
        type StateType is (ST0, ST1, ST2, ST3);
        variable State : StateType;
    begin
	if (Reset ='1') then
            State := ST0;
        elsif rising_edge(Clock) then
            case State is
		when ST0 =>  State := ST1;
		when ST1 =>
		    if (Control ='1') then  State := ST2;
                    else                    STate := ST3;
		    end if;
                when ST2 =>  State := ST3;
		when ST3 =>  State := ST0;
		when others => State := ST0;
            end case;
	end if;
	case State is
	    when ST0 =>    Y <=1;
	    when ST1 =>    Y <=2;
	    when ST2 =>    Y <=3;
            when ST3 =>    Y <=4;
	    when others => Y <=1;
        end case;
    end process ALL_IN_1;
end architecture RTL;