library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FSM2BAD is
    port (Clock, Reset   : in  std_logic;
	  Control        : in  std_logic;
	  Y              : out integer range 1 to 4);
end entity FSM2BAD;

architecture RTL of FSM2BAD is
begin
    ALL_IN_1: process (Clock, Reset)
	type StateType is (ST0, ST1, ST2, ST3);
	variable STATE : StateType := ST0;
    begin
	if (Reset ='1') then
	    Y <= 1;
	    STATE := ST0;
        elsif rising_edge(Clock) then 
	    case (STATE) is
		when ST0 =>  Y <= 1;
			     STATE := ST1;
                when ST1 =>  Y <= 2;
			     if (Control ='1') then
				  STATE := ST2;
                             else STATE := ST3;
			     end if;
                when ST2 =>  Y <= 3;
			     STATE := ST3;
                when ST3 =>  Y <= 4;
			     STATE := ST0;
            end case;
        end if;
    end process ALL_IN_1;
end architecture;