library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity TEST_FSM21 is
end entity TEST_FSM21;

architecture TESTBENCH of TEST_FSM21 is
    component FSM21
	port ( Clock, Reset  : in  std_logic;
	       Control       : in  std_logic;
	       Y             : out integer range 0 to 4);
    end component;
    constant ClockPeriod  : TIME := 20 ns;  
    signal Clock, Reset   : std_logic := '0';
    signal Control        : std_logic;
    signal Y              : integer range 0 to 4;
    signal cycles         : integer := 0;

begin
    -- clock generation
    CLOCK_GEN: process
    begin
	if (cycles < 100) then  -- max 100 cycles
	     cycles <= cycles +1;
	     wait for ClockPeriod / 2;
	     Clock <= not Clock;
        else wait;
	end if;
    end process CLOCK_GEN;

    -- device under test
    U0: FSM21 port map (Clock, Reset, Control, Y);

    process begin
	Reset <= '1';
	wait for (ClockPeriod);
	Reset <= '0'; Control <= '0';
	wait for (ClockPeriod *8);
	Control <= '1';
	wait for (ClockPeriod *8);
	wait;
    end process;

end architecture TESTBENCH;

configuration CFG_FSM21 of TEST_FSM21 is
    for TESTBENCH
    end for;
end configuration CFG_FSM21;