library IEEE;
use IEEE.std_logic_1164.all;

entity  ADDER_TEST  is
end ADDER_TEST;

architecture TESTBENCH of ADDER_TEST  is
component FULL_ADDER
      port ( A, B, CIN    : in  std_logic;
	     S, CO        : out std_logic);
end component;
signal  IN1, IN2, CARRY_IN, S, CO  :  std_logic;
begin
    U0: FULL_ADDER port map (IN1, IN2, CARRY_IN, S, CO);
    process begin
	IN1<='0' ; IN2<='0' ; CARRY_IN<='0';
	wait for 10 ns;
	IN1<='0' ; IN2<='1' ; CARRY_IN<='0';
	wait for 10 ns;
	IN1<='1' ; IN2<='0' ; CARRY_IN<='1';
	wait for 10 ns;
	IN1<='1' ; IN2<='1' ; CARRY_IN<='1';
	wait for 10 ns;
	IN1<='1' ; IN2<='1' ; CARRY_IN<='0';
	wait;
    end process;
end TESTBENCH;