library IEEE;
use IEEE.std_logic_1164.all;

entity HALF_ADDER is
    port  (  A, B        : in  std_logic;
	     S, CO       : out std_logic);
end HALF_ADDER;

architecture  DATAFLOW  of  HALF_ADDER  is
signal  C, D   : std_logic;
begin
    C   <= A or B;
    D   <= A nand B;
    CO  <= not D;
    S   <= C and D;
end DATAFLOW;