library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity COMB is
    port ( A, B, C : IN  std_logic;
	   F, G    : OUT std_logic );
end COMB;

architecture RTL of COMB is
    signal INDATA  : unsigned (2 downto 0);
    signal OUTDATA : unsigned (1 downto 0);
begin

INDATA <= A & B & C;
F <= OUTDATA(0);
G <= OUTDATA(1);

process(INDATA) begin
    case INDATA is
	when "000" => OUTDATA <= "01";
	when "001" => OUTDATA <= "00";
	when "010" => OUTDATA <= "01";
	when "011" => OUTDATA <= "01";
	when "100" => OUTDATA <= "01";
	when "101" => OUTDATA <= "00";
	when "110" => OUTDATA <= "11";
	when "111" => OUTDATA <= "11";
	when others => OUTDATA <= "XX";
    end case;
end process;

end RTL;