library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

entity TEST_COMB is
end entity TEST_COMB;

architecture TESTBENCH of TEST_COMB is
component COMB
    port ( A, B, C : IN  std_logic;
	   F, G    : OUT std_logic );
end component;
    signal INPUT  : unsigned (2 downto 0);
    signal OUTPUT : unsigned (1 downto 0);
begin
    U0: COMB port map (INPUT(2), INPUT(1), INPUT(0), OUTPUT(1), OUTPUT(0));

    process begin
	wait for 10 ns;
	INPUT <= "000"; 
	wait for 10 ns;
	INPUT <= "001"; 
	wait for 10 ns;
	INPUT <= "010"; 
	wait for 10 ns;
	INPUT <= "011"; 
	wait for 10 ns;
	INPUT <= "100"; 
	wait for 10 ns;
	INPUT <= "101"; 
	wait for 10 ns;
	INPUT <= "110"; 
	wait for 10 ns;
	INPUT <= "111"; 
	wait for 10 ns;
	INPUT <= "XXX"; 
	wait;
    end process;
end architecture TESTBENCH;

configuration CFG_COMB of TEST_COMB is
    for TESTBENCH
    end for;
end CFG_COMB;