library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

entity ADDMUL is
    port (Input    : in  unsigned (7 downto 0);
	  GetInput : in  std_logic;
	  Clk      : in  std_logic;
	  Output   : out unsigned (7 downto 0) );
end entity ADDMUL;

architecture RTL of ADDMUL is
    signal  Q  : unsigned (7 downto 0);
begin
    process(Clk)
	variable A   : unsigned (7 downto 0);
    begin 
        if rising_edge(Clk) then  
             ----------
             -- MUX
             ----------
             MUX: if (GetInput = '1') then
                   A := Input;
             else  A := Q;
             end if MUX;
             ----------
	     -- ADD1 & MUL2
	     ----------
	     Q <= Shift_left((A + 1),1);
        end if;
    end process;

    Output <= Q;
end architecture RTL;