Library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

entity TEST_ADDMUL is
end entity TEST_ADDMUL;

architecture TESTBENCH of TEST_ADDMUL is
    constant  ClockPeriod : TIME := 20 ns;
    signal    SystemClk   : std_logic := '0';
    signal    Input       : unsigned(7 downto 0);
    signal    GetInput    : std_logic;
    signal    Output      : unsigned(7 downto 0);
    component ADDMUL
	port (Input    : in  unsigned(7 downto 0);
	      GetInput : in  std_logic;
	      Clk      : in  std_logic;
	      Output   : out unsigned (7 downto 0) );
    end component;
begin
    -- system clock generation
    SystemClk <= not SystemClk after ClockPeriod / 2;
--    SystemClk <= not SystemClk after 10 ns;

    -- Device Under Test
    U1: ADDMUL port map (Input, GetInput, SystemClk, Output);

    process begin
	GetInput <= '0';
	wait for (ClockPeriod);
	Input <= "00000001"; GetInput <= '1';
	wait for (ClockPeriod);
	GetInput <='0';
	wait for (ClockPeriod *2);
	Input <= "00000010"; GetInput <= '1';
	wait for (ClockPeriod);
	GetInput <= '0';
	wait for (ClockPeriod *2);
	Input <= "00001010"; GetInput <= '1';
	wait for (ClockPeriod);
	GetInput <= '0';
	wait for (ClockPeriod *2);
	wait for (ClockPeriod *2);
	wait;
    end process;
end architecture TESTBENCH;

configuration CFG_ADDMUL of TEST_ADDMUL is
    for TESTBENCH
    end for;
end CFG_ADDMUL;