library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FSM22 is
    port ( Clock, Reset  : in  std_logic;
	   Control       : in  std_logic;
	   Y             : out integer range 0 to 4 );
end entity FSM22;

architecture RTL of FSM22 is
    type StateType is (ST0, ST1, ST2, ST3);
    signal STATE : StateType;
begin
    ----------------------
    -- CURRENT STATE & NEXT STATE LOGIC
    ----------------------
    NEXT_CURR: process (Clock, Reset)
    begin
	if (Reset ='1') then
	    STATE <= ST0;
        elsif rising_edge(Clock) then
	    case (STATE) is
		when ST0 => STATE <= ST1;
		when ST1 =>
		    if (Control ='1') then STATE <= ST2;
		    else                   STATE <= ST3;
		    end if;
                when ST2 => STATE <= ST3;
		when ST3 => STATE <= ST0;
		when others => null;
            end case;
       end if;
    end process NEXT_CURR;

    ----------------------
    -- OUTPUT LOGIC (Moore type)
    ----------------------
    with STATE select
	Y <= 1 when ST0,
	     2 when ST1,
	     3 when ST2,
	     4 when ST3,
	     1 when others;

end architecture RTL;