library IEEE;
use IEEE.std_logic_1164.all;

-- テストベンチのエンティティは空
entity TESTBENCH_HA is
end TESTBENCH_HA;

architecture SIM_DATA of TESTBENCH_HA is

-- 検証対象回路(コンポーネント)の宣言
component HALF_ADDER
    port ( A, B : in    std_logic;
           S, C : out   std_logic );
end component;

signal SA, SB, SS, SC : std_logic;

begin
    -- 検証対象回路のインスタンス化
    M1 : HALF_ADDER port map (SA, SB, SS, SC);
    -- テストベクトル
    P1 : process
    begin
        SA <= '0'; wait for 50 ns;
        SA <= '1'; wait for 50 ns;
    end process;
    P2 : process
    begin
        SB <= '0'; wait for 100 ns;
        SB <= '1'; wait for 100 ns;
    end process;
end SIM_DATA;

-- configuration宣言(最上位階層では必須)
configuration CFG_HA of TESTBENCH_HA is
    for SIM_DATA
    end for;
end CFG_HA;