library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity LOOPF is
  port (
    CLK    : in  std_logic;
    RESET  : in  std_logic;
    SIN    : in  std_logic_vector(7 downto 0);  -- <8,0,t>
    SOUT   : out std_logic_vector(11 downto 0) ); -- <12,4,t>
end LOOPF;

architecture RTL of LOOPF is

signal sum    : std_logic_vector(11 downto 0); -- <12,4,t> 
signal dff    : std_logic_vector(11 downto 0); -- <12,4,t>
signal shift  : std_logic_vector(11 downto 0); -- <12,4,t>
signal sub    : std_logic_vector(11 downto 0);  -- <12,4,t>

begin
-- ADDER
   sum <= signed(sub)+signed(SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN);

-- DFF
  process(CLK, RESET) begin 
    if(RESET = '1') then
        dff <= "000000000000";
    elsif(CLK'event and CLK = '1') then
        dff <= sum;
    end if;
  end process;

-- 4 bit shifter
  shift <= dff(11)&dff(11)&dff(11)&dff(11)&dff(11 downto 4);

-- SUBTRACTER
  sub <= signed(dff) - signed(shift);

-- OUTPUT 
  SOUT <= dff;

end RTL;