library STD, IEEE;
use STD.TEXTIO.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;

entity TESTBENCH_LOOPF is
end TESTBENCH_LOOPF;

architecture SIM_DATA of TESTBENCH_LOOPF is

component LOOPF is
  port (
    CLK    : in  std_logic;
    RESET  : in  std_logic;
    SIN    : in  std_logic_vector(7 downto 0);  -- <8,0,t>
    SOUT   : out std_logic_vector(11 downto 0) ); -- <12,4,t>
end component;

signal FMINPUT : std_logic_vector(7 downto 0); -- <8,0,t>
signal LOOPOUT : std_logic_vector(11 downto 0);-- <12,4,t>

signal CLK        : std_logic := '1';
signal RESET      : std_logic := '1';

signal FMINPUT_REAL   : real;
signal LOOPOUT_REAL   : real;

begin

-- CLOCK GENERATION
  CLK <= not CLK after 5 ns;

-- RESET release
  P1: process begin
      RESET <= '1';
      wait for 20 ns;
      RESET <= '0';
      wait;
  end process;

-- TEST VECTOR
  P2: process
      file TEST_IN  : text is in "fm.txt";
      variable LINE_IN : line;
      variable V_FMINPUT : std_logic_vector(7 downto 0);
  begin
      readline(TEST_IN, LINE_IN);
      read(LINE_IN, V_FMINPUT);
      FMINPUT <= V_FMINPUT;
      wait for 10 ns;
      if endfile(TEST_IN) then
        wait;
      end if;
  end process;

-- DUT
  U1: LOOPF port map (CLK, RESET, FMINPUT, LOOPOUT);

-- MONITOR 
FMINPUT_REAL <= real(CONV_INTEGER(signed(FMINPUT))) /128.0;
LOOPOUT_REAL <= real(CONV_INTEGER(signed(LOOPOUT))) /128.0;

end SIM_DATA;

configuration CFG_LOOPF of TESTBENCH_LOOPF is
  for SIM_DATA
  end for;
end CFG_LOOPF;