library STD, IEEE;
use STD.TEXTIO.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;

entity TESTBENCH_MULT is
end TESTBENCH_MULT;

architecture SIM_DATA of TESTBENCH_MULT is

component MULT
  port(in1     : in  std_logic_vector(7 downto 0);
       in2     : in  std_logic_vector(7 downto 0);
       outp    : out std_logic_vector(7 downto 0));
end component;

signal FMINPUT    : std_logic_vector(7 downto 0); -- <8,0,t>
signal MULTOUT    : std_logic_vector(7 downto 0); -- <8,0,t>

signal FMINPUT_I  : integer;
signal FMINPUT_R  : real;
signal FMINPUT_R2 : real;
signal MULTOUT_I  : integer;
signal MULTOUT_R  : real;
signal MULTOUT_R2 : real;

begin

-- DUT
  U1: MULT port map (FMINPUT, FMINPUT, MULTOUT);

-- TEST VECTOR
  P1: process
      file TEST_IN  : text is in "fm.txt";
      variable LINE_IN : line;
      variable V_FMINPUT : std_logic_vector(7 downto 0);
  begin
      readline(TEST_IN, LINE_IN);
      read(LINE_IN, V_FMINPUT);
      FMINPUT <= V_FMINPUT;
      wait for 10 ns;
      if endfile(TEST_IN) then
        wait;
      end if;
  end process;

FMINPUT_I <= CONV_INTEGER(signed(FMINPUT)) ;
FMINPUT_R <= real(FMINPUT_I) /128.0;
FMINPUT_R2<= real(CONV_INTEGER(signed(FMINPUT))) /128.0;
MULTOUT_I <= CONV_INTEGER(signed(MULTOUT)) ;
MULTOUT_R <= real(MULTOUT_I) /128.0;
MULTOUT_R2<= real(CONV_INTEGER(signed(MULTOUT))) /128.0;

end SIM_DATA;

configuration CFG_MULT of TESTBENCH_MULT is
  for SIM_DATA
  end for;
end CFG_MULT;