library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

entity MULT is
  port(in1     : in  std_logic_vector(7 downto 0);
       in2     : in  std_logic_vector(7 downto 0);
       outp    : out std_logic_vector(7 downto 0));
end MULT;

architecture RTL of MULT is

begin

-- SIGNED CLIP ROUND MULTIPLIER
-- in1  <8,0,t>
-- in2  <8,0,t>
-- outp <8,0,t>
  MULT : process(in1,in2)
    variable  var_outp   : std_logic_vector(7 downto 0);  -- <8,0,t>
    variable  var_tprod  : std_logic_vector(15 downto 0); -- <16,1,t>
    variable  var_vtrun  : std_logic_vector(8 downto 0);  -- <9,1,t>
    variable  var_rndbit : std_logic;                     -- <1,1,u>
    variable  var_vext   : std_logic_vector(9 downto 0);  -- <10,2,t>
    variable  var_vext_1 : std_logic_vector(9 downto 0);  -- <10,2,t>
    variable  var_tinc   : std_logic_vector(9 downto 0);  -- <10,2,t>
    variable  var_vrnd   : std_logic_vector(9 downto 0);  -- <10,2,t>
    variable  var_vovflo : std_logic_vector(7 downto 0);  -- <8,0,t> 
  begin
    var_tprod := signed(in1) * signed(in2);
    var_vtrun := var_tprod(15 downto 7);
  -- ROUND 
    var_rndbit := '0';
    if (var_tprod(6) = '1') then
      var_rndbit := '1';
    end if;
    var_vext   := var_vtrun(8) & var_vtrun;
    var_vext_1 := var_vtrun(8) & var_vtrun;
    var_tinc   := signed(var_vext_1) + '1';
    if (var_rndbit = '1') then
      var_vrnd := var_tinc;
    else
      var_vrnd := var_vext;
    end if;
  -- CLIP (IF OVERFLOW then take MAXVALUE)
  --      (IF UNDERFLOW then take MINVALUE)
    var_vovflo := var_vrnd(7 downto 0);
    if (var_vrnd(9 downto 7) /= (var_vrnd(9)&var_vrnd(9)&var_vrnd(9))) then
      var_vovflo := (7=>var_vrnd(9),others=>(not var_vrnd(9)));
    end if;
  -- generate output
    var_outp   := var_vovflo;
    outp <= var_outp;
  end process MULT;

end RTL;