library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity TESTBENCH_NCO is
end TESTBENCH_NCO;

architecture SIM_DATA of TESTBENCH_NCO is

component NCO is
  port (
    CLK    : in  std_logic;
    RESET  : in  std_logic;
    DELTA  : in  std_logic_vector(11 downto 0);  -- <12,-6,t>
    OFFSET : in  std_logic_vector(16 downto 0); -- <17, 0,u>
    COSOUT : out std_logic_vector(7 downto 0) ); -- <8,0,t>
end component;

signal OFFSET : std_logic_vector(16 downto 0); 
signal DELTA  : std_logic_vector(11 downto 0);
signal COSOUT : std_logic_vector(7 downto 0);

signal CLK        : std_logic := '1';
signal RESET      : std_logic := '1';

signal COSOUT_REAL   : real;
signal OFFSET_REAL   : real;
signal DELTA_REAL    : real;
signal COSOUT_OFFSET : std_logic_vector(7 downto 0);

begin

-- CLOCK GENERATION
  CLK <= not CLK after 5 ns;

-- RESET release
  P1: process begin
      RESET <= '1';
      wait for 20 ns;
      RESET <= '0';
      wait;
  end process;

-- DATA VALUE
  P2: process begin
      OFFSET <= "00010000000000000"; -- 1/16
      DELTA  <= "011111111111";      --  +0.0156 (+1/64)
      wait for 1000 ns;
      DELTA  <= "100000000000";      --  -0.0156 (-1/64)
      wait for 1000 ns;
      DELTA  <= "011111111111";      --  +0.0156 (+1/64)
      wait;
  end process;

-- DUT
  U1: NCO port map (CLK, RESET, DELTA, OFFSET, COSOUT);

-- MONITOR 
COSOUT_REAL <= real(CONV_INTEGER(signed(COSOUT))) /128.0;
OFFSET_REAL <= real(CONV_INTEGER(signed(OFFSET))) /2.0**17;
DELTA_REAL  <= real(CONV_INTEGER(signed(DELTA))) /2.0**17;
COSOUT_OFFSET <= (not COSOUT(7)) & COSOUT(6 downto 0);

end SIM_DATA;

configuration CFG_NCO of TESTBENCH_NCO is
  for SIM_DATA
  end for;
end CFG_NCO;