library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

entity EXTVAL is
  port(in1     : in  std_logic_vector(7 downto 0);
       in2     : in  std_logic_vector(7 downto 0);
       outp    : out std_logic_vector(7 downto 0));
end EXTVAL;

architecture RTL of EXTVAL is

signal abs1, abs2   : std_logic_vector(7 downto 0);
signal minval       : std_logic_vector(7 downto 0);
signal signp        : std_logic;

begin

    U_abs1: process(in1) begin
        if(in1(7) /= '0') then
          if(in1(7 downto 0) = "10000000") then
            abs1 <= "01111111";
          else
            abs1 <= - signed(in1) ;
          end if;    
        else
          abs1 <= in1;
        end if;
    end process;

    U_abs2: process(in2) begin
        if(in2(7) /= '0') then
          if(in2(7 downto 0) = "10000000") then
            abs2 <= "01111111";
          else
            abs2 <= - signed(in2) ;
          end if;    
        else
          abs2 <= in2;
        end if;
    end process;

    U_min: process(abs1, abs2) begin
        if(abs1 >= abs2) then 
            minval <= abs2;
        else
            minval <= abs1;
        end if;
    end process;

    signp <= in1(7) xor in2(7);

    U_out: process(signp, minval) begin
        if (signp /= '0') then
            outp <= - signed(minval);
        else
            outp <= minval;
        end if;
    end process;

end RTL;