library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity TESTBENCH_EXTVAL is
end TESTBENCH_EXTVAL;

architecture SIM_DATA of TESTBENCH_EXTVAL is

component EXTVAL
  port(in1     : in  std_logic_vector(7 downto 0);
       in2     : in  std_logic_vector(7 downto 0);
       outp    : out std_logic_vector(7 downto 0));
end component;

signal INPUT1    : std_logic_vector(7 downto 0); 
signal INPUT2    : std_logic_vector(7 downto 0); 
signal OUTP      : std_logic_vector(7 downto 0); 


begin

-- DUT
  U1: EXTVAL port map (INPUT1,INPUT2,OUTP);

-- TEST VECTOR
  P1: process begin
      INPUT1 <= "00000011"; INPUT2 <= "11111111";
      wait for 10 ns;
      INPUT1 <= "00000000"; INPUT2 <= "01111111";
      wait for 10 ns;
      INPUT1 <= "10000000"; INPUT2 <= "10000000";
      wait for 10 ns;
      INPUT1 <= "01111111"; INPUT2 <= "01111111";
      wait for 10 ns;
      INPUT1 <= "01111111"; INPUT2 <= "00111111";
      wait for 10 ns;
      INPUT1 <= "11110000"; INPUT2 <= "00111111";
      wait for 10 ns;
      INPUT1 <= "00001111"; INPUT2 <= "11110111";
      wait for 10 ns;
      INPUT1 <= "00001111"; INPUT2 <= "00001001";
      wait for 10 ns;
      wait;
  end process;

end SIM_DATA;

configuration CFG_EXTVAL of TESTBENCH_EXTVAL is
  for SIM_DATA
  end for;
end CFG_EXTVAL;