library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity SPC is
  port(CLK         : in  std_logic;
       START       : in  std_logic;
       RXIN        : in  std_logic_vector(7 downto 0);
       Y0,Y1,Y2,Y3 : out std_logic_vector(7 downto 0);
       R0,R1,C0,C1 : out std_logic_vector(7 downto 0) );
end SPC;

architecture RTL of SPC is

signal S1,S2,S3,S4,S5,S6,S7,S8         : std_logic_vector(7 downto 0);

begin

-- SHIFT REGISTER
  process(CLK) begin
    if (CLK'event and CLK = '1') then
        S8 <= RXIN;
        S7 <= S8;
        S6 <= S7;
        S5 <= S6;
        S4 <= S5;
        S3 <= S4;
        S2 <= S3;
        S1 <= S2;
    end if;
  end process;

--  OUTPUT REGISTER
  process(CLK) begin
    if (CLK'event and CLK='1') then
        if (START = '1') then
            Y0 <= S1;
            Y1 <= S2;
            Y2 <= S3;
            Y3 <= S4;
            R0 <= S5;
            R1 <= S6;
            C0 <= S7;
            C1 <= S8;
        end if;        
    end if;
  end process;

end RTL;