library STD, IEEE;
use STD.TEXTIO.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;

entity TESTBENCH_SPC is
end TESTBENCH_SPC;

architecture SIM_DATA of TESTBENCH_SPC is

component SPC 
  port(CLK         : in  std_logic;
       START       : in  std_logic;
       RXIN        : in  std_logic_vector(7 downto 0);
       Y0,Y1,Y2,Y3 : out std_logic_vector(7 downto 0);
       R0,R1,C0,C1 : out std_logic_vector(7 downto 0) );
end component;


signal START       : std_logic;
signal RXIN        : std_logic_vector(7 downto 0);
signal Y0,Y1,Y2,Y3 : std_logic_vector(7 downto 0);
signal R0,R1,C0,C1 : std_logic_vector(7 downto 0);
signal CLK         : std_logic := '0';

begin

-- Sysetem CLK generation
      CLK <= not CLK after 5 ns;

-- DUT
  U1: SPC port map (CLK,START,RXIN,Y0,Y1,Y2,Y3,R0,R1,C0,C1 );

-- TEST VECTOR
  P1: process
      file TEXT1_IN     : text is in "start.txt";
      file TEXT2_IN     : text is in "rxin100DB.txt";
      variable LINE1_IN : line;
      variable LINE2_IN : line;
      variable V_START  : std_logic;
      variable V_RXIN   : std_logic_vector(7 downto 0);
  begin
      readline(TEXT1_IN, LINE1_IN);
      read(LINE1_IN, V_START);
      START <= V_START;
      readline(TEXT2_IN, LINE2_IN);
      read(LINE2_IN, V_RXIN);
      RXIN <= V_RXIN;
      wait for 10 ns;
      if endfile(TEXT1_IN) then
        wait;
      end if;
  end process;



end SIM_DATA;

configuration CFG_SPC of TESTBENCH_SPC is
  for SIM_DATA
  end for;
end CFG_SPC;