library IEEE;
use IEEE.std_logic_1164.all;
-- below library supports std_logic_vector operations
use IEEE.std_logic_unsigned.all;

entity ADDER4 is
    port ( A, B : in  std_logic_vector(3 downto 0);
           S    : out std_logic_vector(4 downto 0));
end ADDER4;

architecture BEHAVIOR of ADDER4 is
begin
    S  <= ('0' & A) + ('0' & B);
end BEHAVIOR;