library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity MULT8x8 is
    port ( A, B : in  std_logic_vector(7 downto 0);
           M    : out std_logic_vector(15 downto 0));
end MULT8x8;

architecture RTL of MULT8x8 is
begin
    M  <= A * B;
end RTL;