library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

--  testbench entity is empty
entity TESTBENCH_MULT8x8 is
end TESTBENCH_MULT8x8;

architecture SIM_DATA of TESTBENCH_MULT8x8 is

-- component declaration
component MULT8x8
    port ( A, B : in  std_logic_vector(7 downto 0);
           M    : out std_logic_vector(15 downto 0));
end component;

signal SA, SB : std_logic_vector(7 downto 0);
signal SM     : std_logic_vector(15 downto 0);

begin
    -- design under test
    M1 : MULT8x8 port map (SA, SB, SM);
    -- test vector
    P1 : process
    begin
       for I in 0 to 255 loop
           for J in 0 to 255 loop
               SA <= conv_std_logic_vector(I,8);
               SB <= conv_std_logic_vector(J,8);
               wait for 10 ns;
           end loop;
       end loop;
    end process;
end SIM_DATA;

-- configuration
configuration CFG_MULT8x8 of TESTBENCH_MULT8x8 is
    for SIM_DATA
    end for;
end CFG_MULT8x8;