-- Small Risk Processor SRP
-- supported instructions : LW, SW, ADD, SUB, AND, OR, SLT, BEQ, J
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

use WORK.ALU_PKG.all;

entity SRP is
    port ( Clock   : in  std_logic;
	   Reset   : in  std_logic;               -- reset when it is '1' 
	   Iadd    : out std_logic_vector (5 downto 0);   -- Address for IROM
	   Inst    : in  std_logic_vector (31 downto 0);  -- Instruction from IROM
	   Dadd    : out std_logic_vector (5 downto 0);   -- Address for DRAM
	   WE      : out std_logic;               -- DRAM Write Enable
           Wtdata  : out std_logic_vector (31 downto 0);  -- Write data to DRAM
	   Rddata  : in  std_logic_vector (31 downto 0) );  -- Read data from DRAM
end entity SRP;

architecture RTL of SRP is

-- WRITE YOUR CODE 

end architecture RTL;