-- Synchronous Data RAM
-- 5 address inputs, 1 clock input and 1 WriteEnable input 
-- 32 data inputs and 32 data outputs 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

use WORK.ALU_PKG.all;

entity DRAM is
    port ( Add    : in  std_logic_vector (5 downto 0);
	   Clock  : in  std_logic;
	   WE     : in  std_logic;
	   Din    : in  std_logic_vector (31 downto 0);
	   Dout   : out std_logic_vector (31 downto 0) );
end entity DRAM;

architecture RTL of DRAM is
    type MemVecArr is array (0 to 63) of std_logic_vector (31 downto 0);
    -----------------------------
    -- Data RAM
    -----------------------------
    signal RAM  : MemVecArr  := 
    (0 => conv_std_logic_vector ( 0, 32),  -- array(0)
     1 => conv_std_logic_vector ( 1, 32),  -- array(1)
     2 => conv_std_logic_vector ( 2, 32),  -- array(2)
     3 => conv_std_logic_vector ( 3, 32),  -- array(3)
     4 => conv_std_logic_vector ( 4, 32),  -- array(4)
     5 => conv_std_logic_vector ( 5, 32),  -- array(5)
     6 => conv_std_logic_vector ( 6, 32),  -- array(6)
     7 => conv_std_logic_vector ( 7, 32),  -- array(7)
     8 => conv_std_logic_vector ( 8, 32),  
     9 => conv_std_logic_vector ( 9, 32),
    10 => conv_std_logic_vector (10, 32),
    11 => conv_std_logic_vector (11, 32),
    12 => conv_std_logic_vector (12, 32),
    13 => conv_std_logic_vector (13, 32),
    14 => conv_std_logic_vector (14, 32),
    15 => conv_std_logic_vector (15, 32),
    16 => conv_std_logic_vector (16, 32),
    17 => conv_std_logic_vector (17, 32),
    18 => conv_std_logic_vector (18, 32),
    19 => conv_std_logic_vector (19, 32),
    20 => conv_std_logic_vector (20, 32),
    21 => conv_std_logic_vector (21, 32),
    22 => conv_std_logic_vector (22, 32),
    23 => conv_std_logic_vector (23, 32),
    24 => conv_std_logic_vector (24, 32),
    25 => conv_std_logic_vector (25, 32),
    26 => conv_std_logic_vector (26, 32),
    27 => conv_std_logic_vector (27, 32),
    28 => conv_std_logic_vector (28, 32),
    29 => conv_std_logic_vector (29, 32),
    30 => conv_std_logic_vector (30, 32),
    31 => conv_std_logic_vector (31, 32),  
    32 => conv_std_logic_vector (256,32),   -- start byte address of the array
    33 => conv_std_logic_vector (32 ,32),   -- size of array in byte, 8 word
    34 => conv_std_logic_vector (4,  32),   -- size of word in byte
    others => conv_std_logic_vector ( 0, 32) ); 
begin
    READ_OP: 
	Dout <= RAM ( conv_integer(Add) ) after 10 ns;
	
    WRITE_OP: process (Clock)
    begin
        if (rising_edge(Clock)) then
            if (WE = '1') then RAM ( conv_integer(Add) ) <= Din;
	    end if;
	end if;
    end process WRITE_OP;

end architecture RTL;