library IEEE;
use IEEE.std_logic_1164.all;
-- below library is needed for conv_std_logic_vector()
use IEEE.std_logic_arith.all;

--  testbench entity is empty
entity TESTBENCH_HA is
end TESTBENCH_HA;

architecture SIM_DATA of TESTBENCH_HA is

-- component declaration
component ADDER4
    port ( A, B : in  std_logic_vector(3 downto 0);
           S    : out std_logic_vector(4 downto 0));
end component;

signal SA, SB : std_logic_vector(3 downto 0);
signal SS     : std_logic_vector(4 downto 0);

begin
    -- design under test
    M1 : ADDER4 port map (SA, SB, SS);
    -- test vector
    P1 : process
    begin
       for I in 0 to 15 loop
           for J in 0 to 15 loop
               SA <= conv_std_logic_vector(I,4);
               SB <= conv_std_logic_vector(J,4);
               wait for 10 ns;
           end loop;
       end loop;
    end process;
end SIM_DATA;

-- configuration
configuration CFG_ADDER4 of TESTBENCH_HA is
    for SIM_DATA
    end for;
end CFG_ADDER4;