library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


entity dctALL is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           R0 : in  STD_LOGIC_VECTOR (7 downto 0);
           R1 : in  STD_LOGIC_VECTOR (7 downto 0);
           R2 : in  STD_LOGIC_VECTOR (7 downto 0);
           R3 : in  STD_LOGIC_VECTOR (7 downto 0);
           R4 : in  STD_LOGIC_VECTOR (7 downto 0);
           R5 : in  STD_LOGIC_VECTOR (7 downto 0);
           R6 : in  STD_LOGIC_VECTOR (7 downto 0);
           R7 : in  STD_LOGIC_VECTOR (7 downto 0);
           valid_input : in  STD_LOGIC;
           Q0 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q1 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q2 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q3 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q4 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q5 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q6 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q7 : out  STD_LOGIC_VECTOR (7 downto 0);
           valid_output : out  STD_LOGIC);
end dctALL;

architecture Behavioral of dctALL is

component oneDCT is
    Port ( RC0 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC1 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC2 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC3 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC4 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC5 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC6 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC7 : in  STD_LOGIC_VECTOR (15 downto 0);
           H0 : out  STD_LOGIC_VECTOR (15 downto 0);
           H1 : out  STD_LOGIC_VECTOR (15 downto 0);
           H2 : out  STD_LOGIC_VECTOR (15 downto 0);
           H3 : out  STD_LOGIC_VECTOR (15 downto 0);
           H4 : out  STD_LOGIC_VECTOR (15 downto 0);
           H5 : out  STD_LOGIC_VECTOR (15 downto 0);
           H6 : out  STD_LOGIC_VECTOR (15 downto 0);
           H7 : out  STD_LOGIC_VECTOR (15 downto 0));
end component;

signal R00, R01, R02, R03, R04, R05, R06, R07 : std_logic_vector(7 downto 0); -- <8,8,u>
signal R10, R11, R12, R13, R14, R15, R16, R17 : std_logic_vector(7 downto 0); -- <8,7,t>
signal RB0, RB1, RB2, RB3, RB4, RB5, RB6, RB7 : std_logic_vector(15 downto 0); --<16,11,t>
signal RC0, RC1, RC2, RC3, RC4, RC5, RC6, RC7 : std_logic_vector(15 downto 0); --<16,11,t>
signal H0, H1, H2, H3, H4, H5, H6, H7 : std_logic_vector(15 downto 0); --<16,11,t>

begin

-- INPUT REGISTERS
process (clk) 
begin
 if (clk'event and clk = '1') then
   R00 <= R0;
	R01 <= R1;
	R02 <= R2;
	R03 <= R3;
	R04 <= R4;
	R05 <= R5;
	R06 <= R6;
	R07 <= R7;
 end if;
end process;

-- MSB inverse & REGISTER
process (clk) 
begin
 if (clk'event and clk = '1') then
   R10 <= not(R00(7)) & R00(6 downto 0);
	R11 <= not(R01(7)) & R01(6 downto 0);
	R12 <= not(R02(7)) & R02(6 downto 0);
	R13 <= not(R03(7)) & R03(6 downto 0);
	R14 <= not(R04(7)) & R04(6 downto 0);
	R15 <= not(R05(7)) & R05(6 downto 0);
	R16 <= not(R06(7)) & R06(6 downto 0);
	R17 <= not(R07(7)) & R07(6 downto 0);
 end if;
end process;

-- <8,7,t> to <16,11,t> bit expand
  RB0 <= R10(7) & R10(7) & R10(7) & R10(7) & R10 & "0000";
  RB1 <= R11(7) & R11(7) & R11(7) & R11(7) & R11 & "0000";
  RB2 <= R12(7) & R12(7) & R12(7) & R12(7) & R12 & "0000";
  RB3 <= R13(7) & R13(7) & R13(7) & R13(7) & R13 & "0000";
  RB4 <= R14(7) & R14(7) & R14(7) & R14(7) & R14 & "0000";
  RB5 <= R15(7) & R15(7) & R15(7) & R15(7) & R15 & "0000";
  RB6 <= R16(7) & R16(7) & R16(7) & R16(7) & R16 & "0000";
  RB7 <= R17(7) & R17(7) & R17(7) & R17(7) & R17 & "0000";
 
-- copy RB* to RC*
  RC0 <= RB0;
  RC1 <= RB1;
  RC2 <= RB2;
  RC3 <= RB3;
  RC4 <= RB4;
  RC5 <= RB5;
  RC6 <= RB6;
  RC7 <= RB7;

-- 1D-DCT
  oneDCT0: oneDCT port map
  (RC0, RC1, RC2, RC3, RC4, RC5, RC6, RC7,
   H0,  H1,  H2,  H3,  H4,  H5,  H6,  H7);


end Behavioral;