-- TestBench Template 

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.std_logic_arith.ALL;

  ENTITY testbench IS
  END testbench;

  ARCHITECTURE behavior OF testbench IS 
  
  component dctALL
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           R0 : in  STD_LOGIC_VECTOR (7 downto 0);
           R1 : in  STD_LOGIC_VECTOR (7 downto 0);
           R2 : in  STD_LOGIC_VECTOR (7 downto 0);
           R3 : in  STD_LOGIC_VECTOR (7 downto 0);
           R4 : in  STD_LOGIC_VECTOR (7 downto 0);
           R5 : in  STD_LOGIC_VECTOR (7 downto 0);
           R6 : in  STD_LOGIC_VECTOR (7 downto 0);
           R7 : in  STD_LOGIC_VECTOR (7 downto 0);
           valid_input : in  STD_LOGIC;
           Q0 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q1 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q2 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q3 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q4 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q5 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q6 : out  STD_LOGIC_VECTOR (7 downto 0);
           Q7 : out  STD_LOGIC_VECTOR (7 downto 0);
           valid_output : out  STD_LOGIC);
  end component;
  
  

  type INTMEMORY is array ( 0 to 63 ) of integer;
  constant INPUT : INTMEMORY := (
    139, 144, 149, 153, 155, 155, 155, 155,
    144, 151, 153, 156, 159, 156, 156, 156,
    150, 155, 160, 163, 158, 156, 156, 156,
    159, 161, 162, 160, 160, 159, 159, 159,
    159, 160, 161, 162, 162, 155, 155, 155,
    161, 161, 161, 161, 160, 157, 157, 157,
    161, 161, 161, 161, 160, 157, 157, 157,
    162, 162, 161, 161, 163, 158, 158, 158 );
  constant QY : INTMEMORY := (
	 16,  11,  10,  16,  24,  40,  51,  61,
    12,  12,  14,  19,  26,  58,  60,  55,
    14,  13,  16,  24,  40,  57,  69,  56,
    14,  17,  22,  29,  51,  87,  80,  62,
    18,  22,  37,  56,  68,  109, 103, 77,
    24,  35,  55,  64,  81,  104, 113, 92,
    49,  64,  78,  87,  103, 121, 120, 101,
    72,  92,  95,  98,  112, 100, 103, 99 );
  type REALMEMORY is array ( 0 to 63 ) of real;
  constant CF : REALMEMORY := (
  0.3536,  0.3536,  0.3536,  0.3536,  0.3536,  0.3536,  0.3536,  0.3536,
  0.4904,  0.4157,  0.2778,  0.0975, -0.0975, -0.2778, -0.4157, -0.4904,
  0.4619,  0.1913, -0.1913, -0.4619, -0.4619, -0.1913,  0.1913,  0.4619,
  0.4157, -0.0975, -0.4904, -0.2778,  0.2778,  0.4904,  0.0975, -0.4157,
  0.3536, -0.3536, -0.3536,  0.3536,  0.3536, -0.3536, -0.3536,  0.3536,
  0.2778, -0.4904,  0.0975,  0.4157, -0.4157, -0.0975,  0.4904, -0.2778,
  0.1913, -0.4619,  0.4619, -0.1913, -0.1913,  0.4619, -0.4619,  0.1913,
  0.0975, -0.2778,  0.4157, -0.4904,  0.4904, -0.4157,  0.2778, -0.0975 );

  signal clk   : std_logic := '0';
  signal reset : std_logic := '1';
  signal R0, R1, R2, R3, R4, R5, R6, R7 : std_logic_vector (7 downto 0);
  signal valid_input : std_logic := '0';
  signal Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 : std_logic_vector (7 downto 0);
  signal valid_output : std_logic := '0';

  BEGIN

  -- Sysetem CLK generation
      clk <= not clk after 5 ns;

  -- DUT
  dctALL0: dctALL port map (
           clk,reset,
           R0,R1,R2,R3,R4,R5,R6,R7,
           valid_input,
			  Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,
			  valid_output);
  
  -- INPUT signals
  process begin
	wait for 20 ns;
	  reset <= '0'; 
	wait for 10 ns;
	  valid_input <= '1'; 
	  for I in 0 to 7 loop
	    R0 <= conv_std_logic_vector(INPUT(I),8);
		 R1 <= conv_std_logic_vector(INPUT(I+8),8);
		 R2 <= conv_std_logic_vector(INPUT(I+16),8);
		 R3 <= conv_std_logic_vector(INPUT(I+24),8);
		 R4 <= conv_std_logic_vector(INPUT(I+32),8);
		 R5 <= conv_std_logic_vector(INPUT(I+40),8);
		 R6 <= conv_std_logic_vector(INPUT(I+48),8);
		 R7 <= conv_std_logic_vector(INPUT(I+56),8);
		 wait for 10 ns;
	  end loop;
	  valid_input <= '0';
	  	 R0 <="00000000";
		 R1 <="00000000";
		 R2 <="00000000";
		 R3 <="00000000";
		 R4 <="00000000";
		 R5 <="00000000";
		 R6 <="00000000";
		 R7 <="00000000";
	wait for 10 ns;
	wait;
  end process;

  END;