library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

entity MULTB is
  port(in1     : in  std_logic_vector(15 downto 0);  -- in1  <16,11,t>
       in2     : in  std_logic_vector(15 downto 0);  -- in2  <16, 0,t>
       outp    : out std_logic_vector( 7 downto 0)); -- outp < 8, 7,t>
end MULTB;

architecture RTL of MULTB is

begin

-- SIGNED ROUND MULTIPLIER
  MULTB0 : process(in1,in2)
    variable  var_outp   : std_logic_vector(7 downto 0); -- < 8, 7,t>
    variable  var_tprod  : std_logic_vector(31 downto 0); -- <32,12,t>
    variable  var_vtrun  : std_logic_vector(8 downto 0);  -- < 9, 8,t>
    variable  var_rndbit : std_logic;                     -- <1,1,u>
    variable  var_vext   : std_logic_vector(9 downto 0);  -- <10, 9,t>
    variable  var_vext_1 : std_logic_vector(9 downto 0);  -- <10, 9,t>
    variable  var_tinc   : std_logic_vector(9 downto 0);  -- <10, 9,t>
    variable  var_vrnd   : std_logic_vector(9 downto 0);  -- <10, 9,t>
    
  begin
    var_tprod := signed(in1) * signed(in2);
    var_vtrun := var_tprod(27 downto 19);
  -- ROUND 
    var_rndbit := '0';
    if (var_tprod(18) = '1') then
      var_rndbit := '1';
    end if;
    var_vext   := var_vtrun(8) & var_vtrun;
    var_vext_1 := var_vtrun(8) & var_vtrun;
    var_tinc   := signed(var_vext_1) + '1';
    if (var_rndbit = '1') then
      var_vrnd := var_tinc;
    else
      var_vrnd := var_vext;
    end if;
  -- generate output
    var_outp   := var_vrnd(7 downto 0);
    outp <= var_outp;
  end process MULTB0;

end RTL;