library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity oneDCT is
    Port ( RC0 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC1 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC2 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC3 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC4 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC5 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC6 : in  STD_LOGIC_VECTOR (15 downto 0);
           RC7 : in  STD_LOGIC_VECTOR (15 downto 0);
           H0 : out  STD_LOGIC_VECTOR (15 downto 0);
           H1 : out  STD_LOGIC_VECTOR (15 downto 0);
           H2 : out  STD_LOGIC_VECTOR (15 downto 0);
           H3 : out  STD_LOGIC_VECTOR (15 downto 0);
           H4 : out  STD_LOGIC_VECTOR (15 downto 0);
           H5 : out  STD_LOGIC_VECTOR (15 downto 0);
           H6 : out  STD_LOGIC_VECTOR (15 downto 0);
           H7 : out  STD_LOGIC_VECTOR (15 downto 0));
end oneDCT;

architecture Behavioral of oneDCT is

  type MEMORY16 is array ( 0 to 63 ) of std_logic_vector(15 downto 0);
  -- <16,0,t> array
  constant CF : MEMORY16 := (
  CONV_std_logic_vector(INTEGER(0.3536 * 32768.0),16),  
  CONV_std_logic_vector(INTEGER(0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.4904 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.4157 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.2778 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.0975 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.0975 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.2778 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.4157 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.4904 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.4619 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.1913 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.1913 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.4619 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.4619 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.1913 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.1913 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.4619 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.4157 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.0975 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.4904 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.2778 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.2778 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.4904 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.0975 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.4157 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.3536 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.2778 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.4904 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.0975 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.4157 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.4157 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.0975 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.4904 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.2778 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.1913 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.4619 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.4619 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.1913 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.1913 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.4619 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.4619 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.1913 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.0975 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.2778 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.4157 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.4904 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.4904 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.4157 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(0.2778 * 32768.0),16),
  CONV_std_logic_vector(INTEGER(-0.0975 * 32768.0),16) );
  
  component MULTA
  port(in1     : in  std_logic_vector(15 downto 0);  -- in1  <16,11,t>
       in2     : in  std_logic_vector(15 downto 0);  -- in2  <16, 0,t>
       outp    : out std_logic_vector(15 downto 0)); -- outp <16,11,t>
  end component;

  signal HOUT : MEMORY16;
  
begin

-- H0 
  U0: MULTA port map (RC0, CF(0), HOUT(0));
  U1: MULTA port map (RC1, CF(1), HOUT(1));
  U2: MULTA port map (RC2, CF(2), HOUT(2));
  U3: MULTA port map (RC3, CF(3), HOUT(3));
  U4: MULTA port map (RC4, CF(4), HOUT(4));
  U5: MULTA port map (RC5, CF(5), HOUT(5));
  U6: MULTA port map (RC6, CF(6), HOUT(6));
  U7: MULTA port map (RC7, CF(7), HOUT(7));
  H0 <= signed(HOUT(0))+signed(HOUT(1))+signed(HOUT(2))+signed(HOUT(3))
       +signed(HOUT(4))+signed(HOUT(5))+signed(HOUT(6))+signed(HOUT(7));
--
-- H1 
   U8: MULTA port map (RC0, CF( 8), HOUT( 8));
   U9: MULTA port map (RC1, CF( 9), HOUT( 9));
  U10: MULTA port map (RC2, CF(10), HOUT(10));
  U11: MULTA port map (RC3, CF(11), HOUT(11));
  U12: MULTA port map (RC4, CF(12), HOUT(12));
  U13: MULTA port map (RC5, CF(13), HOUT(13));
  U14: MULTA port map (RC6, CF(14), HOUT(14));
  U15: MULTA port map (RC7, CF(15), HOUT(15));
  H1 <= signed(HOUT( 8))+signed(HOUT( 9))+signed(HOUT(10))+signed(HOUT(11))
       +signed(HOUT(12))+signed(HOUT(13))+signed(HOUT(14))+signed(HOUT(15));
--
-- H2 
  U16: MULTA port map (RC0, CF(16), HOUT(16));
  U17: MULTA port map (RC1, CF(17), HOUT(17));
  U18: MULTA port map (RC2, CF(18), HOUT(18));
  U19: MULTA port map (RC3, CF(19), HOUT(19));
  U20: MULTA port map (RC4, CF(20), HOUT(20));
  U21: MULTA port map (RC5, CF(21), HOUT(21));
  U22: MULTA port map (RC6, CF(22), HOUT(22));
  U23: MULTA port map (RC7, CF(23), HOUT(23));
  H2 <= signed(HOUT(16))+signed(HOUT(17))+signed(HOUT(18))+signed(HOUT(19))
       +signed(HOUT(20))+signed(HOUT(21))+signed(HOUT(22))+signed(HOUT(23));
--
-- H3 
  U24: MULTA port map (RC0, CF(24), HOUT(24));
  U25: MULTA port map (RC1, CF(25), HOUT(25));
  U26: MULTA port map (RC2, CF(26), HOUT(26));
  U27: MULTA port map (RC3, CF(27), HOUT(27));
  U28: MULTA port map (RC4, CF(28), HOUT(28));
  U29: MULTA port map (RC5, CF(29), HOUT(29));
  U30: MULTA port map (RC6, CF(30), HOUT(30));
  U31: MULTA port map (RC7, CF(31), HOUT(31));
  H3 <= signed(HOUT(24))+signed(HOUT(25))+signed(HOUT(26))+signed(HOUT(27))
       +signed(HOUT(28))+signed(HOUT(29))+signed(HOUT(30))+signed(HOUT(31));
--
-- H4 
  U32: MULTA port map (RC0, CF(32), HOUT(32));
  U33: MULTA port map (RC1, CF(33), HOUT(33));
  U34: MULTA port map (RC2, CF(34), HOUT(34));
  U35: MULTA port map (RC3, CF(35), HOUT(35));
  U36: MULTA port map (RC4, CF(36), HOUT(36));
  U37: MULTA port map (RC5, CF(37), HOUT(37));
  U38: MULTA port map (RC6, CF(38), HOUT(38));
  U39: MULTA port map (RC7, CF(39), HOUT(39));
  H4 <= signed(HOUT(32))+signed(HOUT(33))+signed(HOUT(34))+signed(HOUT(35))
       +signed(HOUT(36))+signed(HOUT(37))+signed(HOUT(38))+signed(HOUT(39));
--
-- H5 
  U40: MULTA port map (RC0, CF(40), HOUT(40));
  U41: MULTA port map (RC1, CF(41), HOUT(41));
  U42: MULTA port map (RC2, CF(42), HOUT(42));
  U43: MULTA port map (RC3, CF(43), HOUT(43));
  U44: MULTA port map (RC4, CF(44), HOUT(44));
  U45: MULTA port map (RC5, CF(45), HOUT(45));
  U46: MULTA port map (RC6, CF(46), HOUT(46));
  U47: MULTA port map (RC7, CF(47), HOUT(47));
  H5 <= signed(HOUT(40))+signed(HOUT(41))+signed(HOUT(42))+signed(HOUT(43))
       +signed(HOUT(44))+signed(HOUT(45))+signed(HOUT(46))+signed(HOUT(47));
--
-- H6 
  U48: MULTA port map (RC0, CF(48), HOUT(48));
  U49: MULTA port map (RC1, CF(49), HOUT(49));
  U50: MULTA port map (RC2, CF(50), HOUT(50));
  U51: MULTA port map (RC3, CF(51), HOUT(51));
  U52: MULTA port map (RC4, CF(52), HOUT(52));
  U53: MULTA port map (RC5, CF(53), HOUT(53));
  U54: MULTA port map (RC6, CF(54), HOUT(54));
  U55: MULTA port map (RC7, CF(55), HOUT(55));
  H6 <= signed(HOUT(48))+signed(HOUT(49))+signed(HOUT(50))+signed(HOUT(51))
       +signed(HOUT(52))+signed(HOUT(53))+signed(HOUT(54))+signed(HOUT(55));
--
-- H7 
  U56: MULTA port map (RC0, CF(56), HOUT(56));
  U57: MULTA port map (RC1, CF(57), HOUT(57));
  U58: MULTA port map (RC2, CF(58), HOUT(58));
  U59: MULTA port map (RC3, CF(59), HOUT(59));
  U60: MULTA port map (RC4, CF(60), HOUT(60));
  U61: MULTA port map (RC5, CF(61), HOUT(61));
  U62: MULTA port map (RC6, CF(62), HOUT(62));
  U63: MULTA port map (RC7, CF(63), HOUT(63));
  H7 <= signed(HOUT(56))+signed(HOUT(57))+signed(HOUT(58))+signed(HOUT(59))
       +signed(HOUT(60))+signed(HOUT(61))+signed(HOUT(62))+signed(HOUT(63));
--

end Behavioral;