library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

entity TEST_3_6DEC is
end entity TEST_3_6DEC;

architecture TESTBENCH of TEST_3_6DEC is
component DECODER3_6
    port ( En       : in  std_logic;
	   A        : in  unsigned(2 downto 0);
	   Y        : out unsigned(5 downto 0));
end component;
signal    EIN    : std_logic;
signal    AIN    : unsigned(2 downto 0);
signal    YOUT   : unsigned(5 downto 0);
begin
    U0: DECODER3_6 port map (EIN, AIN, YOUT);
    process begin
        EIN  <= '0';
	wait for 10 ns;
	EIN  <= '1';
	AIN  <= "000";
	wait for 10 ns;
	AIN  <= "001";
	wait for 10 ns;
	AIN  <= "010";
	wait for 10 ns;
	AIN  <= "011";
	wait for 10 ns;
	AIN  <= "100";
	wait for 10 ns;
	AIN  <= "101";
	wait for 10 ns;
	AIN  <= "110";
	wait for 10 ns;
	AIN  <= "111";
	wait for 10 ns;
	wait;
    end process;
end architecture TESTBENCH;

configuration CFG_3_6_DEC of TEST_3_6DEC is
    for TESTBENCH
    end for;
end CFG_3_6_DEC;