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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:09:54 01/24/2012 
-- Design Name: 
-- Module Name:    fft_circuitA - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL; -- TSUIKA

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fft_circuitA is
    Port ( s_re0 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_im0 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_re1 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_im1 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_re2 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_im2 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_re3 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_im3 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_re4 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_im4 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_re5 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_im5 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_re6 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_im6 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_re7 : in  STD_LOGIC_VECTOR (15 downto 0);
           s_im7 : in  STD_LOGIC_VECTOR (15 downto 0);
           G_re0 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_im0 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_re1 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_im1 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_re2 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_im2 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_re3 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_im3 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_re4 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_im4 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_re5 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_im5 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_re6 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_im6 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_re7 : out  STD_LOGIC_VECTOR (15 downto 0);
           G_im7 : out  STD_LOGIC_VECTOR (15 downto 0));
end fft_circuitA;

architecture Behavioral of fft_circuitA is

--s1 signals
signal s1_re0 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_im0 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_re1 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_im1 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_re2 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_im2 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_re3 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_im3 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_re4 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_im4 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_re5 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_im5 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_re6 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_im6 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_re7 :  STD_LOGIC_VECTOR (15 downto 0);
signal s1_im7 :  STD_LOGIC_VECTOR (15 downto 0);
--
signal W8_re1 :  STD_LOGIC_VECTOR (9 downto 0) := "0101101010"; -- +0.7071 in <10,0,t>
signal W8_im1 :  STD_LOGIC_VECTOR (9 downto 0) := "1010010110"; -- -0.7071 in <10,0,t>
--
signal tmp_s1_re5 : STD_LOGIC_VECTOR (25 downto 0);
signal tmp_s1_im5 : STD_LOGIC_VECTOR (25 downto 0);
signal tmp_s1_re7 : STD_LOGIC_VECTOR (25 downto 0);
signal tmp_s1_im7 : STD_LOGIC_VECTOR (25 downto 0);

begin
-- STAGE1
-- s1(0) = s(0) + s(4)
--s1_re(0) <= s_re(0) + s_re(4);
--s1_im(0) <= s_im(0) + s_im(4);
s1_re0 <= s_re0 + s_re4;
s1_im0 <= s_im0 + s_im4;

-- s1(4) = {s(0) - s(4)}*W8**0
--s1_re(4) <= s_re(0) - s_re(4);
--s1_im(4) <= s_im(0) - s_im(4);
s1_re4 <= s_re0 - s_re4;
s1_im4 <= s_im0 - s_im4;

-- s1(1) = s(1) + s(5)
--s1_re(1) <= s_re(1) + s_re(5);
--s1_im(1) <= s_im(1) + s_im(5);
s1_re1 <= s_re1 + s_re5;
s1_im1 <= s_im1 + s_im5;

-- s1(5) = {s(1) - s(5)}*W8**1
--t_re     := s_re(1) - s_re(5);
--t_im     := s_im(1) - s_im(5);
--s1_re(5) <= W8_re(1) * t_re - W8_im(1) * t_im;
--s1_im(5) <= W8_im(1) * t_re + W8_re(1) * t_im;
tmp_s1_re5 <= (W8_re1 * (s_re1 - s_re5)) - (W8_im1 * (s_im1 - s_im5)); 
tmp_s1_im5 <= (W8_im1 * (s_re1 - s_re5)) + (W8_re1 * (s_im1 - s_im5)); 
s1_re5 <= tmp_s1_re5(24 downto 9);
s1_im5 <= tmp_s1_im5(24 downto 9);

-- s1(2) = s(2) + s(6)
--s1_re(2) <= s_re(2) + s_re(6);
--s1_im(2) <= s_im(2) + s_im(6);
s1_re2 <= s_re2 + s_re6;
s1_im2 <= s_im2 + s_im6;

-- s1(6) = {s(2) - s(6)}*W8**2
--W8_re(2) <=  0.0;    W8_im(2) <= -1.0;
--t_re     := s_re(2) - s_re(6);
--t_im     := s_im(2) - s_im(6);
--s1_re(6) <= W8_re(2) * t_re - W8_im(2) * t_im =  t_im;
--s1_im(6) <= W8_im(2) * t_re + W8_re(2) * t_im = -t_re;
s1_re6 <= s_im2 - s_im6;
s1_im6 <= s_re6 - s_re2;

-- s1(3) = s(3) + s(7)
--s1_re(3) <= s_re(3) + s_re(7);
--s1_im(3) <= s_im(3) + s_im(7);
s1_re3 <= s_re3 + s_re7;
s1_im3 <= s_im3 + s_im7;

-- s1(7) = {s(3) - s(7)}*W8**3
--W8_re(3) <= -0.7071; W8_im(3) <= -0.7071;
--t_re     := s_re(3) - s_re(7);
--t_im     := s_im(3) - s_im(7);
--s1_re(7) <= W8_re(3) * t_re - W8_im(3) * t_im=W8_im1 * t_re - W8_im1 * t_im;
--s1_im(7) <= W8_im(3) * t_re + W8_re(3) * t_im=W8_im1 * t_re + W8_im1 * t_im;
tmp_s1_re7 <= W8_im1 * (s_re3 - s_re7 - s_im3 + s_im7);
tmp_s1_im7 <= W8_im1 * (s_re3 - s_re7 + s_im3 - s_im7);
s1_re7 <= tmp_s1_re7(24 downto 9);
s1_im7 <= tmp_s1_im7(24 downto 9);

--
G_re0 <= s1_re0;
G_im0 <= s1_im0;
G_re1 <= s1_re1;
G_im1 <= s1_im1;
G_re2 <= s1_re2;
G_im2 <= s1_im2;
G_re3 <= s1_re3;
G_im3 <= s1_im3;
G_re4 <= s1_re4;
G_im4 <= s1_im4;
G_re5 <= s1_re5;
G_im5 <= s1_im5;
G_re6 <= s1_re6;
G_im6 <= s1_im6;
G_re7 <= s1_re7;
G_im7 <= s1_im7;

end Behavioral;