-- Synopsys Design Contest 2002
-- receiver.vhd
-- 2001/September/10th
-- TASK: Differencial Cyclic Code FEC
-- Copyright by  Tom Wada@Univ. of the Ryukyus

library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

entity RECEIVER is
    port (START    : in  std_logic;
	  RBWE     : in  std_logic;
	  START2   : out std_logic;
	  RBEC     : out std_logic;
	  RESET    : in  std_logic;
	  CLK      : in  std_logic );
end entity RECEIVER;

architecture RTL of RECEIVER is

-- HERE, WRITE YOUR ORIGINAL HDL CODE!

-- GOOD LUCK!


end architecture RTL;