-- Synopsys Design Contest 2002
-- test_dcc21.vhd
-- 2001/September/10th
-- TASK: Differencial Cyclic Code FEC
-- Copyright by  Tom Wada@Univ. of the Ryukyus

library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

entity TEST_DCC21 is
end entity TEST_DCC21;

architecture TESTBENCH of TEST_DCC21 is
    component TRANSMITTER
	port ( SBWE  : out  std_logic;
	       SB    : out  std_logic;
	       START : out  std_logic;
	       RESET : in   std_logic;
	       CLK   : in   std_logic );
    end component;
    component RECEIVER
	port ( START : in   std_logic;
	       RBWE  : in   std_logic;
	       START2: out  std_logic;
	       RBEC  : out  std_logic;
	       RESET : in   std_logic;
	       CLK   : in   std_logic );
    end component;
    component ERRORCNT
	port ( START : in   std_logic;
	       RB    : in   std_logic;
	       START2: in   std_logic;
	       RBEC  : in   std_logic;
	       ERRCNT: out  unsigned(7 downto 0);
	       RESET : in   std_logic;
	       CLK   : in   std_logic );
    end component;
    signal     SBWE   :  std_logic;
    signal     SB     :  std_logic;
    signal     START  :  std_logic;
    signal     RESET  :  std_logic := '1';
    signal     CLK    :  std_logic := '0';
    signal     RBEC   :  std_logic;
    signal     START2 :  std_logic;
    signal     ERRCNT :  unsigned(7 downto 0);
begin
    -- clock generation
    CLK <= not CLK after 10 ns;

    TX: TRANSMITTER port map 
    (SBWE, SB, START, RESET, CLK);

    RX: RECEIVER port map
    (START, SBWE, START2, RBEC, RESET, CLK);

    EC: ERRORCNT port map
    (START,SB,START2,RBEC,ERRCNT,RESET,CLK);

    process 
    begin
        RESET_LOOP: for N in 0 to 3 loop
	wait until falling_edge(CLK);
        end loop RESET_LOOP;
	    RESET <= '0';

	CAL_LOOP: for N in 0 to 500 loop
	wait until falling_edge(CLK);
	end loop CAL_LOOP;

	wait;
    end process;
end architecture TESTBENCH;

configuration CFG_DCC21 of TEST_DCC21 is
    for TESTBENCH 
    end for;
end configuration CFG_DCC21;