-- Univ. of the Ryukyus LSI design contest 2004
-- SubBytes Transform Circuit for AES Cipher
-- file: test_subbytes.vhd
-- TESTBENCH 
-- Tom Wada 2003/September/15

library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

entity TEST_SUBBYTES is
end entity TEST_SUBBYTES;

architecture TESTBENCH of TEST_SUBBYTES is
  -- sender  
  component SENDER 
      port ( CLK    : in  std_logic;  
             RESET  : in  std_logic;
             PLAIN  : out unsigned (7 downto 0) );
  end component SENDER;
  -- subbytes
  component SUBBYTES
      port ( CLK    : in  std_logic;
             RESET  : in  std_logic;
             XIN    : in  unsigned(7 downto 0);
             INV    : in  std_logic;
             YOUT   : out unsigned(7 downto 0) );
  end component SUBBYTES;

-- system clock
signal  CLK  : std_logic  := '0' ;
-- system reset
signal RESET : std_logic  := '1';
-- cycle count
signal cycle : integer :=0;
-- wires on the board
signal PLAIN  : unsigned (7 downto 0);
signal YOUT   : unsigned (7 downto 0);
signal INV    : std_logic  := '0';
 
begin

-- clock generator
    CLOCK_GEN: process
    begin
        if (cycle < 1000) then
            cycle <= cycle + 1;
            wait for 10 ns;
            CLK <= not CLK;
        else wait;
        end if;
    end process CLOCK_GEN;

-- reset sequence
    RESET_GEN: process
    begin
        LOOP1: for N in 0 to 5 loop
           wait until falling_edge(CLK);
        end loop LOOP1;
        RESET <= '0';
    end process RESET_GEN;

-- sender instance
    I_SENDER: SENDER port map(CLK,RESET,PLAIN);

-- subbytes instance
    I_SUBBYTES: SUBBYTES port map(CLK,RESET,PLAIN,INV,YOUT);
 
end architecture TESTBENCH;


configuration CFG_SUBBYTES of TEST_SUBBYTES is
    for TESTBENCH
    end for;
end configuration CFG_SUBBYTES;