-- Synchronous Data RAM
-- 5 address inputs, 1 clock input and 1 WriteEnable input 
-- 32 data inputs and 32 data outputs 
-- Tom Wada 1999/7
library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

use WORK.ALU_PKG.all;

entity DRAM is
    port ( Add    : in  unsigned (5 downto 0);
	   Clock  : in  std_logic;
	   WE     : in  std_logic;
	   Din    : in  unsigned (31 downto 0);
	   Dout   : out unsigned (31 downto 0) );
end entity DRAM;

architecture RTL of DRAM is
    type MemVecArr is array (0 to 63) of unsigned (31 downto 0);
    -----------------------------
    -- Data RAM
    -----------------------------
    signal RAM  : MemVecArr  := 
    (0 => TO_UNSIGNED ( 0, 32),  -- array(0)
     1 => TO_UNSIGNED ( 1, 32),  -- array(1)
     2 => TO_UNSIGNED ( 2, 32),  -- array(2)
     3 => TO_UNSIGNED ( 3, 32),  -- array(3)
     4 => TO_UNSIGNED ( 4, 32),  -- array(4)
     5 => TO_UNSIGNED ( 5, 32),  -- array(5)
     6 => TO_UNSIGNED ( 6, 32),  -- array(6)
     7 => TO_UNSIGNED ( 7, 32),  -- array(7)
     8 => TO_UNSIGNED ( 8, 32),  
     9 => TO_UNSIGNED ( 9, 32),
    10 => TO_UNSIGNED (10, 32),
    11 => TO_UNSIGNED (11, 32),
    12 => TO_UNSIGNED (12, 32),
    13 => TO_UNSIGNED (13, 32),
    14 => TO_UNSIGNED (14, 32),
    15 => TO_UNSIGNED (15, 32),
    16 => TO_UNSIGNED (16, 32),
    17 => TO_UNSIGNED (17, 32),
    18 => TO_UNSIGNED (18, 32),
    19 => TO_UNSIGNED (19, 32),
    20 => TO_UNSIGNED (20, 32),
    21 => TO_UNSIGNED (21, 32),
    22 => TO_UNSIGNED (22, 32),
    23 => TO_UNSIGNED (23, 32),
    24 => TO_UNSIGNED (24, 32),
    25 => TO_UNSIGNED (25, 32),
    26 => TO_UNSIGNED (26, 32),
    27 => TO_UNSIGNED (27, 32),
    28 => TO_UNSIGNED (28, 32),
    29 => TO_UNSIGNED (29, 32),
    30 => TO_UNSIGNED (30, 32),
    31 => TO_UNSIGNED (31, 32),  
    32 => TO_UNSIGNED (256,32),   -- start byte address of the array
    33 => TO_UNSIGNED (32 ,32),   -- size of array in byte, 8 word
    34 => TO_UNSIGNED (4,  32),   -- size of word in byte
    others => TO_UNSIGNED ( 0, 32) ); 
begin
    READ_OP: 
	Dout <= RAM ( TO_INTEGER(Add) ) after 10 ns;
	
    WRITE_OP: process (Clock)
    begin
        if (rising_edge(Clock) and WE = '1') then
            RAM ( TO_INTEGER(Add) ) <= Din;
	end if;
    end process WRITE_OP;

end architecture RTL;