library IEEE;
use IEEE.std_logic_1164.all;
-- below library is needed for conv_std_logic_vector()
use IEEE.std_logic_arith.all;

--  testbench entity is empty
entity TESTBENCH_BERT is
end TESTBENCH_BERT;

architecture SIM_DATA of TESTBENCH_BERT is

-- component declaration


component BERT is
        port( RESET : in std_logic;
                CLK : in std_logic; 
                TCK : in std_logic;
                RCK : in std_logic;
                RcvBit : in std_logic;
                RefBit : in std_logic;
                MesSw : in std_logic;
                Sel : in std_logic_vector(2 downto 0);
                Dout : out std_logic_vector(7 downto 0);
                TxD : out std_logic_vector(14 downto 0)
        );
end component;


signal RESET          : std_logic := '0';
signal CLK            : std_logic := '0';
signal RcvBit,RefBit  : std_logic;
signal MesSw          : std_logic := '0';
signal Sel            : std_logic_vector(2 downto 0) := "000";
signal Dout           : std_logic_vector(7 downto 0);
signal TxD            : std_logic_vector(14 downto 0);

signal cycles         : integer :=0;
signal ERROR          : std_logic :='0';

signal PRBS9          : std_logic_vector(8 downto 0);

begin

CLOCK_GEN: process
begin
  if(cycles < 10000) then
      cycles <= cycles +1;
      wait for 50 ns;
      CLK <= not CLK;
  else wait;
  end if;
end process CLOCK_GEN;

RESET_SEQ: process
begin
    wait for 100 ns;
    RESET <= '1';
end process RESET_SEQ;

BERT1: BERT port map (RESET, CLK, CLK, CLK, RcvBit, RefBit, MesSw,
                      Sel, Dout, TxD);

MEASURE_START: process
begin
    wait for 200 ns;
    MesSw <= '1';
end process MEASURE_START;

RefBit <= TxD(0);
RcvBit <= TxD(1) xor ERROR;


-- ERROR GENERATOR --
process(CLK,RESET) begin
if (RESET='0') then PRBS9 <= "111111111";
elsif (CLK'event and CLK='1') then
    PRBS9(8) <= PRBS9(5) xor PRBS9(0);
    for I in 0 to 7 loop
      PRBS9(I) <= PRBS9(I+1);
    end loop;
end if;
end process;

ERROR <= PRBS9(0);


end SIM_DATA;

-- configuration
configuration CFG_BERT of TESTBENCH_BERT is
    for SIM_DATA
    end for;
end CFG_BERT;