-- Synopsys design contest 2000
-- Wada's VHDL design 1999/12/28
library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

entity GFMATMULT is
    port ( GET    : in  std_logic;
	   IN1    : in  unsigned(3 downto 0);
	   IN2    : in  unsigned(3 downto 0);
	   IN3    : in  unsigned(3 downto 0);
	   ADD    : in  unsigned(3 downto 0);
	   ELE    : in  unsigned(3 downto 0);
	   WE     : in  std_logic;
	   CLK    : in  std_logic;
	   RESET  : in  std_logic;
	   DONE   : out std_logic;
	   OUT1   : out unsigned(3 downto 0);
	   OUT2   : out unsigned(3 downto 0);
	   OUT3   : out unsigned(3 downto 0) );
end entity GFMATMULT;

architecture RTL of GFMATMULT is

-- Here write your description!

begin

-- Here write your description!

end architecture RTL;