-- TESTBENCH for minimips (small instruction set MIPS machine)
-- Tom Wada 1999/7

library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

use WORK.ALU_PKG.all;

entity TEST_MINIMIPS is
end entity TEST_MINIMIPS;

architecture TESTBENCH of TEST_MINIMIPS is
  -- instruction read only memory IROM
    component IROM
	port (Add   : in  unsigned (5 downto 0);
	      Dout  : out unsigned (31 downto 0) );
    end component IROM;
  -- data random access memory DRAM
    component DRAM
	port (Add   : in  unsigned (5 downto 0);
	      Clock : in  std_logic;
	      WE    : in  std_logic;
	      Din   : in  unsigned (31 downto 0);
	      Dout  : out unsigned (31 downto 0) );
    end component DRAM;
  -- minimips
    component MINIMIPS
	port (Clock    : in  std_logic;
	      Reset    : in  std_logic;
	      Iadd     : out unsigned (5 downto 0);
	      Inst     : in  unsigned (31 downto 0);
	      Dadd     : out unsigned (5 downto 0);
	      WE       : out std_logic;
	      Wtdata   : out unsigned (31 downto 0);
	      Rddata   : in  unsigned (31 downto 0) );
    end component MINIMIPS;
  -- system clock
    signal  Clock  : std_logic := '0';
  -- system reset
    signal  Reset  : std_logic := '1';
  -- wires on the board
    signal  Iadd   : unsigned (5 downto 0);
    signal  Inst   : unsigned (31 downto 0);
    signal  Dadd   : unsigned (5 downto 0);
    signal  WE     : std_logic;
    signal  Wtdata : unsigned (31 downto 0);
    signal  Rddata : unsigned (31 downto 0);
    
begin
  -- clock generator while Iadd is less than 24.
    CLOCK_GEN: process 
    begin
	if (Iadd /=  TO_UNSIGNED(24,6)) then
	    wait for 50 ns;
	    Clock <= not Clock;
        else wait;
        end if;
    end process CLOCK_GEN;
  -- IROM
    ROM: IROM port map (Iadd,Inst);
  -- DRAM
    RAM: DRAM port map (Dadd,Clock,WE,Wtdata,Rddata);
  -- MINIMIPS MPU
    MPU: MINIMIPS port map (Clock,Reset,Iadd,Inst,Dadd,WE,Wtdata,Rddata);
  -- reset sequence
    RESET_SEQ: process
    begin
        LOOP1: for N in 0 to 5 loop
            wait until falling_edge(Clock);
	end loop LOOP1;
	Reset <= '0';
    end process RESET_SEQ;
end architecture TESTBENCH;

configuration CFG_MINIMIPS of TEST_MINIMIPS is
    for TESTBENCH
    end for;
end configuration CFG_MINIMIPS;