library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity TEST_ALU is
end TEST_ALU;

architecture TESTBENCH of TEST_ALU is
component ALU
    port ( Sel      : in   std_logic_vector(4 downto 0);
           CarryIn  : in   std_logic;
           A, B     : in   std_logic_vector(7 downto 0);
           Y        : out  std_logic_vector(7 downto 0));
end component;
signal    SIN           : std_logic_vector(4 downto 0);
signal    CIN           : std_logic;
signal    AIN,BIN,YIN   : std_logic_vector(7 downto 0);
begin
        U0: ALU port map (SIN,CIN,AIN,BIN,YIN);
        process begin
            AIN <= "00001111";  BIN <= "11110000";
            wait for 10 ns;
            SIN <= "00000"; CIN <= '0';
            wait for 10 ns;
            SIN <= "00000"; CIN <= '1';
            wait for 10 ns;
            SIN <= "00001"; CIN <= '0';
            wait for 10 ns;
            SIN <= "00001"; CIN <= '1';
            wait for 10 ns;
            SIN <= "00010"; CIN <= '0';
            wait for 10 ns;
            SIN <= "00010"; CIN <= '1';
            wait for 10 ns;
            SIN <= "00011"; CIN <= '0';
            wait for 10 ns;
            SIN <= "00011"; CIN <= '1';
            wait for 10 ns;
            SIN <= "00100"; CIN <= '0';
            wait for 10 ns;
            SIN <= "00101"; CIN <= '0';
            wait for 10 ns;
            SIN <= "00110"; CIN <= '0';
            wait for 10 ns;
            SIN <= "00111"; CIN <= '0';
            wait for 10 ns;
            SIN <= "01000"; CIN <= '0';
            wait for 10 ns;
            SIN <= "10000"; CIN <= '0';
            wait for 10 ns;
            SIN <= "11000"; CIN <= '0';
            wait for 10 ns;
            wait;

        end process;
end TESTBENCH;

configuration CFG_ALU of TEST_ALU is
    for TESTBENCH
    end for;
end CFG_ALU;