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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:17:23 10/05/2011 
-- Design Name: 
-- Module Name:    counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
    Port ( sysclk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           output : out  STD_LOGIC_VECTOR (3 downto 0));
end counter;

architecture Behavioral of counter is
signal intcount : std_logic_vector (27 downto 0);
begin

process(sysclk, reset) begin
	if (reset = '0') then
		intcount <= "0000000000000000000000000000";
	elsif (sysclk'event and sysclk='1') then
		intcount <= intcount + '1';
	end if;
end process;

output <= intcount(27 downto 24);
--output <= "1010";

end Behavioral;