=============== addressing mode =============== address *address dircet, extend ,X *X indexed 1,Y *(Y+1) offset (8bit, 16bit) ,S++ *(S++) post-increment = pop 2byte ,--U *(--U) pre-decrement = push 2byte ,S+ *(S+) post-increment = pop 1byte ,-U *(-U) pre-decrement = push 1byte A,U *(U+A) register offset = array access B,S *(S+B) register offset D,X *(X+D) register offset 10,PCR *(10,pc) program counter relative [address] **address indirect (for all addressing) ========== load store ========== LD load from memory LDA #1 LDB ,S+ = POPS B LDD ,X++ LDS #$2030 LDU data ST store to memory STA ,-U = PSHU A STD ,--U = PUSH D STS #$2030 STU data LEA load effective address LEAX 1,X X = X+1 LEAY D,X Y = D+X LEAU ,S U=S (is faster than TFR S,U) LEAS -5,S S = S-5 LEA sets Z flag TFR transfer register to register TFR A,B B = A TFR S,U U = S EXG exchange registers EXG A,CC A< => CC EXG X,D X< => D PSH push PSHS D = STD ,--S PSHU Y,X = STY ,--U;STY ,--U POP pop POPS A,PC = LDA ,S+; RTS POPU A = LDA ,U+ ========== compuation ========== ABX add B to X ADC add with carry ADCA data A = A + *data + carry ADCB #$10 B = B + 0x10 + carry ADCA ,X A = A + *X no ADCD ADD add ADDA ,X A = A + *X ADDB data B = B + *data ADDB #$20 B = B + 0x20 ADDD ,Y++ D = D + *Y++ ADDD #$1020 D = D + 0x1020 AND and ANDA #10 A &= 0xa ANDB address B &= *address ASL arithmetic shift left ASLA ASLB ASL 10,X ASR arithmetic shift right ASRA ASRB ASL 10,X CMP compare CMPA 10,X A > *(X+10) CMPB ,Y B > *Y CMPD 10,X D > *(X+10) COM complement COMA A ^= 0xff COMB B ^= 0xff COM 10,X *(X+10) ^= 0xff CLR clear, store 0 CLRA A = 0 CLRB B = 0 CLR 10,X *(X+10) = 0 DEC decrement DECA A -- DECB B -- DEC 10,X *(X+10) = *(X+10)-1 EOR exclusiv or EORA #10 A ^= 0xa EORB address B ^= *address EORA 10,X A = A ^ *(X+10) INC increment INCA A ++ INCB B ++ INC 10,X *(X+10) = *(X+10)+1 LSL logical shift left LSR logical shift right MUL multiply D = A * B NEG negation NEGA A = -A NEGB B = -B NEG 10,X *(X+10) = -*(X+10) OR or ORA #10 A |= 0xa ORB address B |= *address ORA 10,X A = A | *(X+10) ROL rotate left ROR rotate right SEX sign extend SUB subtract SUBA #10 A -= 0xa SUBB address B -= *address SUBD 10,X D = D - *(X+10) SBC subtract with carry SBCA #10 A -= 0xa - carry SBCB address B -= *address - carry TST test, compare with 0 TSTA A > 0 TSTB B > 0 TST 10,X *(X+10) > 0 ====== branch ====== BSR relative branch subroutine (8bit offset) LBSR long relative branch subroutine (16bit offset) JMP absoulte jump JSR absolute branch subroutine RTS return from subroutine Bxx brach condition (8bit offset) LBxx long branch (16bit offset) simple BRA branch always BRN branch never simple conditional BMI branch minous BPL branch minous BEQ branch on zero BNE branch on non zero BVS branch on overflow BVS branch on non overflow BCS branch on carry set BCC branch on carry clear signed conditional BGT r> m BGE r> =m BEQ r==m BNE r!=m BLE r< =m BLT r< m unsigned conditional BHI r> m BHS r> =m BEQ r==m BNE r!=m BLO r< m BLS r< =m ============= miscellaneous ============= DAA decimal adjust CWAI clear cc and wait for interrupt NOP no operation RTI return from interrupt SWI software interrupt, system call SYNC synchronize to external event