****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
        -sort_by group
Design : ADDER4
Version: Z-2007.03
Date   : Mon Nov  5 04:11:57 2007
****************************************

Operating Conditions: 
Wire Load Model Mode: top

  Startpoint: B[0] (input port)
  Endpoint: S[4] (output port)
  Path Group: default
  Path Type: max

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  ADDER4             05x05                 class

  Point                                    Incr       Path
  -----------------------------------------------------------
  input external delay                     0.00       0.00 f
  B[0] (in)                                0.00       0.00 f
  U27/Z (ND2I)                             0.25       0.25 r
  U30/Z (ND2I)                             0.19       0.44 f
  U35/Z (AO2P)                             0.98       1.42 r
  U14/Z (ND2I)                             0.33       1.75 f
  U36/Z (AO2P)                             0.98       2.74 r
  U18/Z (AN2I)                             0.34       3.08 r
  U8/Z (AO4)                               0.40       3.48 f
  S[4] (out)                               0.00       3.48 f
  data arrival time                                   3.48

  max_delay                                0.00       0.00
  output external delay                    0.00       0.00
  data required time                                  0.00
  -----------------------------------------------------------
  data required time                                  0.00
  data arrival time                                  -3.48
  -----------------------------------------------------------
  slack (VIOLATED)                                   -3.48