-- 2003 Synopsys silicon sea-belt design contest task -- Variable-Length Decoder for Static Huffman Code -- file: test_vld.vhd -- TESTBENCH module. -- Tom Wada 2002/September/12 library IEEE; use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all; entity TEST_VLD is end entity TEST_VLD; architecture TESTBENCH of TEST_VLD is -- data sender component SENDER port ( CLK : in std_logic; RESET : in std_logic; LOAD : out std_logic; CODE : out unsigned (3 downto 0) ); end component SENDER; -- system clock signal CLK : std_logic := '0' ; -- system reset signal RESET : std_logic := '1'; -- cycle count signal cycle : integer :=0; -- wires on the board signal LOAD : std_logic; signal CODE : unsigned (3 downto 0); begin -- clock generator CLOCK_GEN: process begin if (cycle < 1000) then cycle <= cycle + 1; wait for 10 ns; CLK <= not CLK; else wait; end if; end process CLOCK_GEN; -- reset sequence RESET_GEN: process begin LOOP1: for N in 0 to 5 loop wait until falling_edge(CLK); end loop LOOP1; RESET <= '0'; end process RESET_GEN; -- sender instance I_SENDER: SENDER port map(CLK,RESET,LOAD,CODE); end architecture TESTBENCH; configuration CFG_VLD of TEST_VLD is for TESTBENCH end for; end configuration CFG_VLD;