-- Univ. of the Ryukyus LSI design contest 2004 -- SubBytes Transform Circuit for AES Cipher -- file: sender.vhd -- Sender generates 8 bit integer from 0 to 255 -- Tom Wada 2003/September/15 library IEEE; use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all; entity SENDER is port ( CLK : in std_logic; RESET : in std_logic; PLAIN : out unsigned (7 downto 0) ); end entity SENDER; architecture RTL of SENDER is -- signal define signal count : unsigned (7 downto 0); -- 8 bit counter begin ------------------------------------------- -- 8 bit counter ------------------------------------------- COUNTER: process(CLK) begin if rising_edge(CLK) then if (RESET='1') then count <= "00000000"; else count <= count + 1; end if; end if; end process COUNTER; ------------------------------------------- -- OUTPUT GEN ------------------------------------------- PLAIN <= count; end architecture RTL;